Digital SOC Architect and Design Engineer

Location: Plantation, FL
Date Posted: 11-08-2017
Employment Type:    Full Time Perm - US Citizen or Green Card

 
KEY SKILLS/EXPERIENCE (MUST HAVE)
1.      10+ years of experience in electrical engineering IC and wireless product development
2.      10 years of wireless product development experience including a strong demonstrated record of IC level digital design required with some analog design experience desired
3.      Successful concept to production development experience of mixed signal IC for wireless applications is required
4.      Experience with 1 or more of the following wireless protocols: LTE, UMTS, EVDO, CDMA, iDEN, WLAN, Bluetooth, P25, or TETRA
5.      Experience designing in some of the following areas required: PLL, DAC, ADC, AGC, DSP filter functions, SAR, SPI, QSPI, SSI
6.      Experience integrating 3rd party IP including: customized uP cores, buss controllers, memory controllers, SRAM, eDRAM
7.      Experience with frontend synthesis and backend physical design and verification
8.      Experience with System Verilog / UVM universal verification methodologies
9.      The candidate must be proficient in the following engineering and computer tools:
Windows and Linux operating systems
Microsoft Office Tools (Outlook, MS Word, Excel, PowerPoint, Visio)
Cadence Allegro 16.5 or higher(Schematic-Entry, Constraint Manager and PCB Layout)
Cadence Virtuoso, Synopsys, System Verilog, Verilog, LabView
10.  Code RTL for baseband digital and signal processing designs in Verilog
11.  Contribute to top level microprocessor architecture, integration, and evaluation
12.  Assess 3rd party digital IP
13.  Drive Synopsys tools for synthesis, scan insertion, formal verification, and timing analysis
14.  Drive Cadence Encounter place and route tools to generate a GDS output, coordinate digital chip assembly and execute the physical verification sign-off flow
15.  Work with 180nm down to 40nm CMOS processes
16.  Define test plans, determine applicable specifications at the system & block level for the validation and certification phase, review and compile data into comprehensive reports
17.  Determine areas of risks and determine technical mitigation tasks


Job Description
• Code RTL for baseband digital and signal processing designs in Verilog.• Contribute to top level microprocessor architecture, integration, and evaluation.• Assess 3rd party digital IP.• Drive Synopsys tools for synthesis, scan insertion, formal verification, and timing analysis.• Drive Cadence Encounter place and route tools to generate a GDS output, coordinate digital chip assembly and execute the physical verification sign-off flow.• Work with 180nm down to 40nm CMOS processes.• Define test plans, determine applicable specifications at the system & block level for the validation and certification phase, review and compile data into comprehensive reports. • Determine areas of risks and determine technical mitigation tasks.• Support the product team during integration of ICs into the MSI products.• Work collaboratively within a small world wide multi-discipline engineering team (EE, SW, ME), IP suppliers, and foundries.• Standard business hours are 8am to 4:30pm. • Good verbal & written communication skills. • Some global travel may be required.

Basic Requirements
Bachelor’s Degree
• 10+ years of experience in electrical engineering IC and wireless product development
BSEE required, MSEE preferred with a minimum of 10 years of wireless product development experience including a strong demonstrated record of IC level digital design required with some analog design experience desired.
• Successful concept to production development experience of mixed signal IC for wireless applications is required.
• Experience with 1 or more of the following wireless protocols: LTE, UMTS, EVDO, CDMA, iDEN, WLAN, Bluetooth, P25, or TETRA
• Experience designing in some of the following areas required: PLL, DAC, ADC, AGC, DSP filter functions, SAR, SPI, QSPI, SSI.
• Experience integrating 3rd party IP including: customized uP cores, buss controllers, memory controllers, SRAM, eDRAM.
• Experience with frontend synthesis and backend physical design and verification.
• Experience with System Verilog / UVM universal verification methodologies.
• The candidate must be proficient in the following engineering and computer tools:
Windows and Linux operating systems
Microsoft Office Tools (Outlook, MS Word, Excel, PowerPoint, Visio)
Cadence Allegro 16.5 or higher(Schematic-Entry, Constraint Manager and PCB Layout)
Cadence Virtuoso, Synopsys, System Verilog, Verilog, LabView
 
 
 
 
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